E6H6101

Electronics

Assignment

2

Part

1

Combinational

and Digital Logic

Introduction

8-bit adder design

making needs 1-bit adder, 4-bit adder and 8-bit adder. 1-bit adder VHDL code

can be made by full adder logic circuit. And then 4-bit adder code is produced

by port mapping of 1-bit adder. Finally, 8-bit adder is designed with test

benches programs.

Discussion

Full adder – 1-bit

adder

VHDL entity for a 1-bit adder with carry

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity

fulladder is

Port ( A : in

STD_LOGIC;

B : in

STD_LOGIC;

Cin : in

STD_LOGIC;

S : out

STD_LOGIC;

Cout : out

STD_LOGIC);

end fulladder;

architecture

gate_level of fulladder is

begin

S A,

B => B,

Cin =>

Cin,

S => S,

Cout =>

Cout

);

stim_proc:

process

begin

wait for 100

ns;

A ‘0’);

signal B : std_logic_vector(3 downto 0) := (others

=> ‘0’);

signal Cin : std_logic := ‘0’;

signal S :

std_logic_vector(3 downto 0);

signal Cout : std_logic;

BEGIN

uut: 4bitAdder PORT MAP (

A => A,

B => B,

Cin => Cin,

S => S,

Cout => Cout

);

stim_proc:

process

begin

wait for 100 ns;

A

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state

if input = ‘1’ then state state state state state state state state state state state state state state state state state state state state state